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If you ran the multi pattern and now that you explained the Daly I kind of remember it (I'm old and it's been awhile)I'm as lost as you as to why no sync head to head.

Did you try putting one of the T-berds in repeat mode?


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I honestly don't know the specifics as to why it will run over an open to a hard loop...it's just one of those things. I guess I should rephrase that and say a hard loop right on-top of an open. If you want to test this further, setup everything like you did today but instead of putting the hard loop at the test package, put a hard loop at the end of a few hundred feet of i.w., with the other end hooked into your test package. That should give you errors.

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Originally posted by whynot:
put a hard loop at the end of a few hundred feet of i.w., with the other end hooked into your test package. That should give you errors.
I will try that next time and see what happens. I don't believe it was open because I tested all four pins. When you mentioned that above I thought it could be so I tested them and I seem to have good solid short (1ohm) looking into the card from RJ48 demarc, there was something defenitely wrong with the card I think it was messing up the framing after further testing. It maybe one of those type troubles that I can't explain, just have to except (that is hard for me to do). Thanks again for all the input from you guys.


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Were these new T1's or exsisting T1's that went down?


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What PM information were you able to pull from the card?


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Originally posted by John Osvatic:
What PM information were you able to pull from the card?
I was able to pull all of the pm that you normally get from a Westell 3116 (which is not nearly as much as the Adtran H2 & H4's). The level's looked good in and out. It was coming in around -15 or -16 & coming out @ 0.00 on S1. Going in in -1 from CPE & out of card on S2 @ 0.00. CV, ES, SES, etc. All looked normall. This was a working cicuit that we monitored and it looked like it was up and working fine, but customer wouldn't except it because when they ran head to head it would pass. And sure enough they were right it wouldn't, but it was an otherwise perfect cicuit as far as I can tell from monitoring, and testing intrusive to a hard loop, and from looking at the stats on the card.


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I looked at the scematic of the 3116. There is a lot of electronics on board that card that could go flaky. Have you called Westell tech support?


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Originally posted by John Osvatic:
I looked at the scematic of the 3116. There is a lot of electronics on board that card that could go flaky. Have you called Westell tech support?
No, I wanted to do that but I haven't had time to follow up on it. I had this happen one other time. After I thought about it awhile, I remembered a T1 that was a state cicuit goint to a router that our BMO department installed and maintain. We got an OOS ticket on the T1 and I did some intrusive testing, and it was good all the way to a hard loop at the end of the Cat5 where it plugs into the router. So I referred it back to BMO. They called me back and told me that it still wasn't working and they had changed out the T1 card on the router. I looked at the T1 again, pulled all the stats everything looked good, you could test multi-pat to a hard loop clean. They must have a bad router, they changed it out and with no change. Turns out that the card was bad even though everything tested perfectly fine. I changed out the card and it came right up. Normally I don't change out cards that test perfectlly good, especially when all the stats look good. But this is another scenario where something similar happened. I didn't try running head to head on that particular circuit. This is the only other time I have seen this happen and it still doesn't make sense how it can run so clean, but won't even setup to the router in this case, or to another T-berd head to head in the first scenario. Still scratching my head on that one.


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The tests you performed are benchmarks for testing and turnup purposes. Percentages say the ciruit SHOULD work as designed if these tests pass. BUT,the only test that counts is "can the customer run their data on it?"


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Originally posted by John Osvatic:
The tests you performed are benchmarks for testing and turnup purposes. Percentages say the ciruit SHOULD work as designed if these tests pass. BUT,the only test that counts is "can the customer run their data on it?"
I understand what you are saying, but I have to respectfully disagree with your logic. These are two very rare examples. Normally when T1 circuits are tested with multiple stress patterns, and all stats and levels are good, the circuit is fine. It's normally a customer issue when everything test good. I can't begin to tell you the number of times I have had to isolate the customer's problem on a reported circuit. So if you used the logic that "it's not good if they can't send data" then most of the time you would be chasing your tail, because normally the problem is on their end when the circuit test perfectly clean. I have an example of that right now. A customer's T1 has been down down for several weeks. They keep saying the are getting timing slips, OOF's, etc. We finally had a vedor meet and showed them the circuit was good. It's coming back from them hitting our 3116 Rcard @ -21, we are handing it off to them around -1. All the other circuits there are coming back to us around -2. Just because they can't send their data doesn't mean it's our problem. Once again I understand what your are trying to say I just disagree with that logic.


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